1. Field of the Invention
The present invention relates to a technique of fabricating resin-molded semiconductor devices by using leadframes, and more particularly to a technique suitable for fabricating non-leaded semiconductor device packages having a structure in which external electrode terminals are exposed on a mounting face thereof instead of sidewise lead protrusion, such as small outline non-leaded (SON) packages and quad flat non-leaded (QFN) packages.
2. Description of the Related Art
Leadframes, produced by forming a metal sheet into a desired pattern through fine blanking or etching, are used in fabrication of resin-molded semiconductor devices. Each leadframe unit portion comprises a tab, which is a pad part for mounting a semiconductor chip, and a plurality of leads having tip ends (inner ends) thereof disposed spacedly around the tab. The tab is supported by tab suspension leads extending from frame parts of the leadframe.
In fabrication of resin-molded semiconductor devices by using leadframes such as mentioned above, a semiconductor chip is secured on the tab of each leadframe unit portion, conductive wires are connected between electrodes of the semiconductor chip and the tip ends of the leads, and then the inner lead area including the conductive wires and the semiconductor chip is sealed with resin to form a package for encapsulation. In this process, unnecessary leadframe parts including any protruding parts of leads and tab suspension leads are cut and removed from the package.
According to a known practice in resin-molded semiconductor device fabrication using leadframes, single-sided molding is made on one side of each leadframe unit portion to form a package having a structure in which external electrode terminals (leads) are exposed on a mounting face thereof while no lead protrusion from the periphery thereof is made. This type of semiconductor device package includes an SON package in which leads are exposed along two side edges of a mounting face thereof and a QFN package in which leads are exposed along four side edges of a mounting face thereof in a quadrangular form.
In Japanese Unexamined Patent Publications No. H10 (1998)-34699 and No. H10 (1998)-70217, there are disclosed fabrication techniques for SON packages. In the former, it has been proposed to provide a technique in which a metal mold is covered with an elastic, heat-resistant release film to prevent occurrence of resin burrs at resin sealing in semiconductor device fabrication. In the latter, it has been proposed to provide a technique in which a groove having a cross-sectional shape of an approximately circular arc is formed on a lead-to-lead surface area of mold resin for elongation of a lead-to-lead insulation distance and for prevention of occurrence of resin burrs on a surface where leads are exposed.
Further, Japanese Unexamined Patent Publication No. H10 (1998)-270603 discloses an area-package-type semiconductor device and a method of fabrication thereof. According to this disclosure, as in fabrication of ball-grid-array semiconductor devices, a semiconductor chip is secured on the surface side of a substrate (resin substrate made of glass epoxy resin or the like), external electrodes are disposed in a grid form on the back side thereof, and the semiconductor chip on the surface side is covered with a resin package part. A plurality of area-package-type semiconductor devices are provided in a row on each substrate.
For preventing the external electrodes from being flawed when the substrates are stacked one on top of another, protrusion parts higher than the height of the resin package part are provided on substrates at two or more corners. Thus, the external electrodes will not come into contact with a resin package part of another semiconductor device at the lower position.
For protecting the external electrodes at the time of substrate stacking, it is required to form at least two protrusion parts crosswise with respect to the longitudinal substrate direction.
Non-leaded semiconductor device packages fabricated by single-sided molding, including SON and QFN packages, are used to meet requirements for reduction in physical size and elimination of deformation of external electrode terminal leads.
Since the terminal exposure side of the non-leaded semiconductor device package is used for mounting, the mounting area thereof is smaller than that of a semiconductor device package of a sidewise lead protrusion type, such as a small outline package (SOP) or a quad flat package (QFP). Therefore, on the non-leaded semiconductor device package, if foreign matter adheres to the leads (external electrode terminals) or the leads are flawed, the mounting reliability thereof is degraded.
Referring to FIGS. 34, 35 and 36, there are shown schematic diagrams of mounting conditions in which a non-leaded semiconductor device 1 is mounted on a wiring board 50 such as a mother board. A lead (external electrode terminal) 4 exposed on a mounting face 3 of a package part 2 of the non-leaded semiconductor device 1 is bonded to a land 52 on the wiring board 50 via a bonding material (solder) 51. On a surface part of the lead 4 (mounting surface), a plating film 54 is provided to enhance the wettability of solder (solderability). In these figures, the plating film 54 is indicated as a solid thick line. The plating film 54 is formed by Pbxe2x80x94Sn soldering or palladium-plating (for avoiding the use of Pb as a soldering material).
In pre-plating, a palladium plating film is formed on a leadframe in advance. In post-plating, the soldering film 54 is formed after molding. In soldering film formation, solder is used as a soldering material. In palladium plating film formation, an alloy material not containing Pb, such as Snxe2x80x94Zn or Snxe2x80x94Ag, is used.
FIG. 34 shows a normal mounting condition in which no abnormality is found in mounting. For example, the solder 51 is formed over the entire mounting surface of the lead 4, and a fillet 55 is formed adequately on the outer end face of the lead 4. In visual inspection, it can be judged that the solderability is good.
As shown in FIG. 35, if a foreign substance 56 adheres to the exposure surface of the lead 4, electrical connection is not provided at a region having the foreign substance 56, which could cause poor continuity.
As shown in FIG. 36, if the exposure surface of the lead 4 is flawed to cause partial missing of the plating film 54, the solder 52 is not formed at a region having no plating film. In this condition, poor continuity is prone to occur due to a decrease in bonding area. In the example shown in FIG. 36, since the region having no plating film due to a flaw on the exposure surface of the lead 4 is located at the outer end side, a fillet is not formed adequately. In visual inspection, it is therefore possible to check for poor bonding. If the exposure surface of the lead 4 is flawed at the inner side thereof, a region having no plating film cannot be detected in visual inspection, i.e., a check for poor continuity cannot be made. This could cause degradation in mounting reliability.
As can be seen from the above, in fabrication of non-leaded semiconductor devices, it is required to prevent partial missing of a plating film due to a foreign substance or a flaw on a mounting surface of any lead.
At the workplace of the inventors, non-leaded semiconductor device packages such as QFN and SON packages are manufactured using metallic matrix-type leadframes. The matrix-type leadframe comprises a plurality of unit patterns (unit leadframe patterns) which are arranged on a plurality of rows and columns in a matrix form. On each unit leadframe pattern of the matrix-type leadframe, one non-leaded semiconductor device is formed. More specifically, a semiconductor chip is secured on the center part of each unit leadframe pattern, conductive wires are bonded between electrodes of the semiconductor chip and the inner ends of leads, and then single-sided molding is made on the semiconductor chip and conductive wires to form a package.
In fabrication of non-leaded semiconductor devices using matrix-type leadframes at the workplace of the inventors, after a package is formed on each unit leadframe pattern, the matrix-type leadframes are stacked one on top of another in cases where they are stored or where they are loaded onto a lead cutting apparatus.
In these cases, each leadframe is placed on the top of an insulating-resin package part on another leadframe. In some situations, a mounting surface of a leadframe comes in contact with a package part on another leadframe at the lower position, causing a flaw or contamination on the mounting surface thereof.
Therefore, the inventors devised an arrangement in which a contact-preventive part higher than the height of each package part is provided so that a mounting surface of a leadframe will not come into contact with a package part on another leadframe at the lower position. For this arrangement, the contact-preventive part is formed in a flow cavity communicating with a cavity of a metal mold used for package molding.
More specifically, the flow cavity is provided for the purpose of preventing air from remaining in the metal mold cavity. In the arrangement devised by the inventors, the height (depth) dimension of the flow cavity is made larger than that of the metal mold cavity, and the contact-preventive part is formed by setting resin in the flow cavity.
In Japanese Unexamined Patent Publication No. H10 (1998)-270603 mentioned above, it has been proposed to provide a technique for preventing occurrence of a flaw on external electrodes on ball-grid-array semiconductor devices.
It has been found, however, that this technique is not applicable without difficulty to fabrication of non-leaded semiconductor devices by using matrix-type leadframes.
To be more specific, according to the disclosure in Japanese Unexamined Patent Publication No. H10 (1998)-270603, ball-grid-array semiconductor devices are fabricated by forming a row of quadrangular resin packages along the longitudinal direction of a long substrate. In embodiment, resin is injected through one corner of a quadrangular cavity to form a resin package, and protrusion parts are formed at positions corresponding to the remaining two or three corners. In an air vent of a transfer metal mold, there is provided a pool area. A protrusion part higher than the height of a resin package part is formed by setting resin in this pool area.
On the matrix-type leadframe, a plurality of packages are formed in a matrix consisting of xe2x80x9cnxe2x80x9d rows by xe2x80x9cmxe2x80x9d columns. Therefore, if the above-mentioned technique of fabricating ball-grid-array semiconductor devices is applied to semiconductor device fabrication using matrix-type leadframes, it is required to feed resin to xe2x80x9cmxe2x80x9d by xe2x80x9cnxe2x80x9d cavities and xe2x80x9c2 or 3xe2x80x9d by xe2x80x9cmxe2x80x9d by xe2x80x9cnxe2x80x9d pool areas for forming packages and protrusion parts. The amount of resin to be fed to a runner extending to each cavity must be increased substantially in this application.
Consequently, a longer period of time is taken to fill resin in a cavity located farther apart from a pot, causing an increase in resin viscosity. A flow of resin having higher viscosity could tilt wires to cause a defect of short-circuiting with an adjacent lead or electrode.
In Japanese Unexamined Patent Publication No. H10 (1998)-270603, since electrodes of a semiconductor chip are connected onto a substrate made of a resin material such as glass epoxy resin by means of face-down bonding, it is not necessary to take into consideration a possible defect of short-circuiting due to wire deformation.
Further, according the conventional method of semiconductor device fabrication, the performance of a transfer mold apparatus must be enhanced for increasing the amount of resin to be injected and for increasing injection pressure. This increases the cost of the transfer mold apparatus, resulting in an increase in the cost of semiconductor device fabrication.
Still further, according to the conventional method of semiconductor device fabrication, two or three protrusion parts are formed per package to increase the amount of resin to be used, resulting in an increase in the cost of semiconductor device fabrication.
Furthermore, where the conventional arrangement in which two or three pool areas are provided per cavity is applied to semiconductor device fabrication using matrix-type leadframes, the size of the leadframe must be increased to form the pool areas. In the technique disclosed in Japanese Unexamined Patent Publication No. H10 (1998)-270603, protrusion parts must be formed on substrates at two or more corners in package molding. Where this technique is applied to semiconductor device fabrication using matrix-type leadframes, it is required to increase the size of each unit leadframe pattern to cause a decrease in frame usage efficiency, resulting in an increase in the cost of semiconductor device fabrication.
Still further, where the technique disclosed in Japanese Unexamined Patent Publication No. H10 (1998)-270603, in which protrusion parts must be formed on substrates at two or more corners in package molding, is applied to semiconductor device fabrication using matrix-type leadframes, the amount of resin to be used is increased to result in an increase in the cost of semiconductor device fabrication.
It is therefore an object of the present invention to provide a method of fabricating non-leaded semiconductor devices having satisfactory mounting performance.
Another object of the present invention is to provide a method of fabricating non-leaded semiconductor devices while preventing occurrence of a flaw and adhesion of a foreign substance on mounting surface parts of external electrode terminals.
A further object of the present invention is to provide a method of fabricating non-leaded semiconductor devices with reduction in cost.
An even further object of the present invention is to provide a method of manufacturing electronic apparatus having excellent quality and high reliability.
The following briefly describes representative features and advantages of the present invention:
(1) In carrying out the present invention and according to one aspect thereof, there is provided a semiconductor device comprising: a package part made of insulating resin; a plurality of terminal leads exposed on a mounting face of the package part; and a plurality of tab suspension leads exposed thereon; wherein outer edges of mounting surfaces of the terminal leads and tab suspension leads disposed at the periphery of the package part have no burrs. The package part contains a semiconductor chip, which is secured on a seat area of a tab supported by the tab suspension leads, and a conductive wire is connected between each electrode of the semiconductor chip and each terminal lead. A plating film is formed on each of the terminal leads and tab suspension leads which are exposed on the mounting face of the package part.
According to another aspect of the present invention, there is provided a method of fabricating the above-mentioned semiconductor device, comprising the steps of:
preparing a matrix-type leadframe containing a matrix of a plurality of unit leadframe patterns, each of which comprises a frame part, a tab located inside the frame part, a plurality of tab suspension leads extending from the frame part to the tab for supporting the tab by the tip ends thereof, and a plurality of terminal leads extending from the frame part toward the tab;
securing a semiconductor chip on the tab;
connecting conductive wires between electrodes of the semiconductor chip and inner end parts of the terminal leads;
performing single-sided molding to encapsulate the semiconductor chip, the conductive wires, and the inner end parts of the terminal leads in an insulating resin package part in a fashion that the terminal leads and tab suspension leads are exposed on a mounting face of the package part; and
cutting the terminal leads and tab suspension leads;
wherein, at the step of the single-sided molding, a contact-preventive part thicker than the package part is formed outside the package part, and at the step of the lead cutting, the contact-preventive part is cut.
Further, according to another aspect of the present invention, after the single-sided molding, plating is performed to form a plating film for mounting at each predetermined region on the matrix-type leadframe.
Still further, according to another aspect of the present invention, at the lead cutting step, the terminal leads and tab suspension leads are cut by means of die-punch cutting in which a punch is driven from the mounting face side of the package part.
In accordance with the above-mentioned aspects of the present invention (1), the following advantageous effects can be provided:
(a) In package formation, the contact-preventive part thicker than the package part is formed outside the package part. Therefore, when the leadframes which have been processed through the single-sided molding are stacked one on top of another, external electrode terminals of a leadframe at the upper position do not come into contact with a package part of another leadframe at the lower position since the contact-preventive part is located between the leadframes at the upper and lower positions, preventing occurrence of a flaw and contamination on the external electrode terminals of the leadframe at the upper position. Thus, a non-leaded semiconductor device having high reliability in mounting can be provided.
(b) Since just one contact-preventive part is formed per package part, the amount of resin to be injected does not increase substantially even where the matrix-type leadframe is used. It is therefore not required to increase a pressure of resin injection significantly for transfer molding, thus not causing particular difficulty in transfer molding. Further, it is possible to use a conventional transfer molding apparatus without modification.
(c) Since the amount of resin to be injected for transfer molding does not increase substantially as mentioned in the above item (b), a possible defect of short-circuiting due to wire deformation in a flow of resin will not occur at a distant cavity to which resin is fed through a runner, thus contributing to improvements in yield and reliability.
(d) Since just one contact-preventive part is formed per package part as mentioned in the above item (b), it is not required to substantially increase the size of each unit leadframe pattern, thus contributing to efficient use of the leadframe.
(e) At the step of cutting the terminal leads and tab suspension leads, since the terminal leads and tab suspension leads are cut by means of die-punch cutting in which the punch is driven from the mounting face side of the package part, cutting burrs will not occur at a cut-line edge on the mounting face side while they may occur at a cut-line edge on the side opposite to the mounting face side. Thus, in addition to improvement in the appearance of a i. fabricated non-leaded semiconductor device, it is possible to obviate occurrence of a mounting defect due to cutting burrs.
(f) The advantageous effects mentioned in the above items (a) to (e) make it possible to reduce the cost of semiconductor device fabrication.
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description with reference to the accompanying drawings.